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PIC16F627A/628A/648A

DS40044B-page 142 Preliminary  2004 Microchip Technology Inc.

TABLE 17-6: CLKOUT AND I/O TIMING REQUIREMENTS

FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

Parameter

No.

Sym Characteristic Min Typ† Max Units

10 TosH2ckL OSC1↑ to CLKOUT↓ PIC16F62X — 75 200* ns

10A PIC16LF62X — — 400* ns

11 TosH2ckH OSC1↑ to CLKOUT↑ PIC16F62X — 75 200* ns

11A PIC16LF62X — — 400* ns

12 TckR CLKOUT rise time PIC16F62X — 35 100* ns

12A PIC16LF62X — — 200* ns

13 TckF CLKOUT fall time PIC16F62X — 35 100* ns

13A PIC16LF62X — — 200* ns

14 TckL2ioV CLKOUT ↓ to Port out valid — — 20* ns

15 TioV2ckH Port in valid before CLKOUT ↑ PIC16F62X Tosc+200 ns* — — ns

PIC16LF62X Tosc+400 ns* — — ns

16 TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns

17 TosH2ioV OSC1↑ (Q1 cycle) to PIC16F62X — 50 150* ns

Port out valid PIC16LF62X — — 300* ns

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time)

100*

200*

——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

VDD

MCLR

Internal

POR

PWRT

Time out

OST

Time out

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

1 2 ... 139 140 141 142 143 144 145 146 147 148 149 ... 167 168

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